FLEXIOSRC=00, EMVSIMSRC=00, SDHCSRC=00, PLLFLLSEL=00, TPMSRC=00, LPUARTSRC=00, TRACECLKSEL=0, RTCCLKOUTSEL=0, FBSL=00, CLKOUTSEL=000, USBSRC=0
System Options Register 2
| RTCCLKOUTSEL | RTC clock out select 0 (0): RTC 1 Hz clock is output on the RTC_CLKOUT pin. 1 (1): RTC 32.768kHz clock is output on the RTC_CLKOUT pin. |
| CLKOUTSEL | CLKOUT select 0 (000): FlexBus CLKOUT 2 (010): Flash clock 3 (011): LPO clock (1 kHz) 4 (100): MCGIRCLK 5 (101): RTC 32.768kHz clock 6 (110): OSCERCLK0 7 (111): IRC 48 MHz clock |
| FBSL | FlexBus security level 0 (00): All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 1 (01): All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 2 (10): Off-chip instruction accesses are disallowed. Data accesses are allowed. 3 (11): Off-chip instruction accesses and data accesses are allowed. |
| TRACECLKSEL | Debug trace clock select 0 (0): MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] 1 (1): Core/system clock |
| PLLFLLSEL | PLL/FLL clock select 0 (00): MCGFLLCLK clock 1 (01): MCGPLLCLK clock 3 (11): IRC48 MHz clock |
| USBSRC | USB clock source select 0 (0): External bypass clock (USB_CLKIN). 1 (1): MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV]. |
| FLEXIOSRC | FlexIO Module Clock Source Select 0 (00): System clock 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| TPMSRC | TPM clock source select 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| LPUARTSRC | LPUART clock source select 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| SDHCSRC | SDHC clock source select 0 (00): Core/system clock. 1 (01): MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): External bypass clock (SDHC0_CLKIN) |
| EMVSIMSRC | EMVSIM Module Clock Source Select 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |